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SystemVerilog Timers Library

Description:

A collection of SystemVerilog timers, including:

  • Countdown timer "idv_timer_sim": a simulation countdown timer
    • This timer behaves like an 'egg timer' for simulation time. (We say simulation time to differentiate from a 'wall time' countdown timer.)
    • This timer can started, stopped, restarted (from stopped time), and reset to the initial time.
    • Use for any situation where you want your sim to stop (or do some activity) after a given amount of simulation time has expired.
    • Use to timeout on a hanging task call: start the timer, call the task, stop the timer; if the task call hangs then the timer alarm will sound.
    • Extend and redefine the alarm() method to define the timer expiration activity (the default is to end the simulation)
  • Watchdog timer "idv_watchdog_sim": a simulation watchdog timer
    • A watchdog timer is a special type of countdown timer that restarts itself on the occurance of a watched event.
    • Use to monitor a system heartbeat -- if the duration between beats gets too long then timeout
    • Use to timeout a hanging bus -- map an interface signal to an event; if it takes to long between events then the bus is hung
    • Like the timer - extend and redefine the alarm() method to define the timer expiration activity (the default is to end the simulation)
  • VMM Implementation: individual extensions of both the timer and the watchdog for vmm (uses vmm_log objects for console messaging)
  • OVM Implementation: individual extensions of both the timer and the watchdog for ovm (uses parent ovm_component for console messaging)

Release Tarball:

IDV Timers: Download button (ver. 1.3.1)

Subversion Repository:

Server: svn.intelligentdv.com
Repository: SVtimers
Browse IDV Timers Source

Doxygen Documentation:

Timers Library Doxygen Documentation

Related Blog Posts:

Timers 1.0.0 Release Announcement
Timers 1.1.1 Release Announcement
Timers 1.2.0 Release Announcement
Timers 1.3.1 Release Announcement

Bug Tracking:

File issues and feature requests here:
Bug Tracking
Project: SVtimers

SystemVerilog Reset Library

Description:

A Randomizable SystemVerilog Reset Transaction / Transactor Library that includes:

  • A Base Library that includes:
    • Reset Transaction Class - idv_rst_trans - describes the DUT reset. The properties allow description of:
      • assertion clock relationship (async/sync)
      • deassertion clock relationship (async/sync)
      • number of cycles that reset is active
      • number of cycles to wait prior to assertion
      • number of cycles to wait after reset (prior to returning from the reset task)
      • for async assert: time from rising edge to assert
      • for async deassert: time from rising edge to deassert
    • Reset Transaction Defaults Class - idv_rst_trans_default - constrains the DUT reset. This class can be extended with the user overriding the constraints or used as an example to be reimplemented with user defined constraints.
    • Reset Bus Functional Model (BFM) Transactor Class - idv_rst_bfm - generates a reset based on the passed reset description
      • do_reset method does the reset based on passed in reset transaction (idv_rst_trans)
      • on construction handle to virtual interface (idv_rst_if) passed in
      • on construction definition of active high/low reset - BFM can generate active high or low reset
    • Reset Bus Functional Monitor Transactor Class - idv_rst_mon - generates a reset transaction (description) based on the monitored interface
      • do_reset method waits for reset to occur on interface and outputs a populated reset transaction object
      • on construction handle to virtual interface (idv_rst_if) passed in
      • on construction definition of active high/low reset - can monitor active high or low reset
      • implementation of monitor is limited to monitoring reset duration; other transaction properties are not populated
    • Reset Interface - idv_rst_if - SystemVerilog Interface
      • module ports (modport) defined for BFM, Monitor, and DUT perspectives
      • clocking block defined for BFM and Monitor - for synchronous activity
  • A VMM implementation of the library that includes:
    • VMM Data Transaction Class - idv_rst_data - a vmm_data extended wrapper around the idv_rst_trans class. Includes implementation of the required vmm_data methods. File also includes macro calls to create the vmm_channel IPC channel and vmm_atomic_gen atomic generator.
    • VMM Xactor BFM Class - idv_rst_bfm_xactor - a vmm_xactor extended wrapper around the idv_rst_bfm class. Includes implementation of the required vmm_xactor methods. Input interconnect with generator uses vmm_channel.
    • VMM Xactor Monitor Class - idv_rst_mon_xactor - a vmm_xactor extended wrapper around the idv_rst_mon class. Includes implementation of the required vmm_xactor methods. Output interconnect with sink uses vmm_channel.
    • VMM Xactor Callbacks Class - idv_rst_xactor_callbacks - a vmm_xactor_callbacks extension with pure virutual pre and post transaction callback methods. Can be appended to either the reset bfm or monitor transactor.
    • VMM Xactor Coverage Callback Class - idv_rst_cov_callback - an implementation of reset coverage - can be appended to either the reset bfm or monitor xactor.
  • A complete VMM environment to test the library, and to serve as an example VMM environment, that includes:
    • TestBench Top - tb_top - the signal layer top - instantiates the DUT, interfaces, and clock generator
    • Environment - env - the environment top - configures and instantiates the generators and transactors; drives the testbench sequence
    • Tests - testXXX - the testcases; each constrains a combination of the environment configuration and/or environment transactions to acheive a goal
    • Testcases - example testcases to drive specific scenarios
See the doxygen for complete documentation of this library.

Release Tarball:

IDV Reset: Download button (ver. 1.0.0)

Subversion Repository:

Server: svn.intelligentdv.com
Repository: SVreset
Browse IDV Reset Source

Doxygen Documentation:

Reset Library Doxygen Documentation

Related Blog Posts:

Reset 1.0.0 Release Announcement

Bug Tracking:

File issues and feature requests here:
Bug Tracking
Project: SVreset

SystemVerilog Examples

Description:

A collection of Compilable / Runable SystemVerilog examples, including:

  • Hello World - outputs hello to the console (really a VCS / Questa makefile example)
  • ...
  • ...

Release Tarball:

Download button (ver. 1.0.0)

Subversion Repository:

Server: svn.intelligentdv.com
Repository: SVexamples
Browse SV Examples Source

Doxygen Documentation:

N/A

Related Blog Posts:

Hello (SystemVerilog) World!

Bug Tracking:

File issues and feature requests here:
Bug Tracking
Project: SVexamples You can also use the bugtracker to upload examples to share!

Doxygen Tools (including a Filter for SystemVerilog)

Description:

A set of scripts to enable the use of Doxygen for Verification, including:

  • Filter script that converts SystemVerilog code into C++ like code that the doxygen source code documenting tool can then use to generate documentation.
  • Support script that builds a doxyfile config file from an input doxyfile template and delta file along with a layout xml file.

Release Tarball:

Doxygen Tools: Download button (ver. 2.6.2)
UVM Documentation Scripts: Download button (ver. 1.0.0)
OVM Documentation Scripts: Download button (ver. 1.8.1)
VMM Documentation Scripts: Download button (ver. 1.6.1)
Teal & Truss Documentation Scripts: Download button (ver. 1.6.0)

Subversion Repository:

Server: svn.intelligentdv.com
Repository: Doxygen
Browse Doxygen Tools Source
Repository: OVMdocs
Browse OVM Documentation Scripts Source
Repository: VMMdocs
Browse VMM Documentation Scripts Source
Repository: TealTrussDocs
Browse Teal & Truss Documentation Scripts Source

Doxygen Documentation:

N/A

Related Blog Posts:

First Release Announcement
1.5.3 Release Announcement
1.5.4 Release Announcement
1.6.4 Release Announcement
2.2.0 Release Announcement
2.2.2 Release Announcement
2.3.0 Release Announcement
2.4.0 Release Announcement
2.5.1 Release Announcement
2.6.0 Release Announcement
2.6.2 Release Announcement

Bug Tracking:

File issues and feature requests here:
Bug Tracking
Project: DoxygenFilterSV

Editor Syntax Files

Description:

SystemVerilog (and Vera) Syntax Files for the following editors: Kate, Crimson, and SciTE
Also includes Syntax File for GeSHi.
If you have an HVL Syntax File for another language or editor - send me an email.

Release Tarballs:

All Editors: Download button (ver. 3.0.2)
Just GeSHi: Download button (ver. 3.0.2)
Just Kate: Download button (ver. 3.0.2)
Just Kate (for 2.x Kate): Download button (ver. 1.0.1)
Just Crimson: Download button (ver. 3.0.2)
Just SciTE: Download button (ver. 3.0.2)

Subversion Repository:

Server: svn.intelligentdv.com
Repository: SyntaxFiles
Browse SyntaxFiles Source

Doxygen Documentation:

N/A

Related Blog Posts:

First Release Announcement
How to Install Crimson Editor Syntax Files
How to Install Kate Syntax Files
How to Install SciTE Syntax Files
Using SciTE "Copy as RTF" to Make Pretty Code in Microsoft Documents and Presentations
Release 3.0.1 Announcement

Bug Tracking:

File issues and feature requests here:
Bug Tracking
Project: SyntaxFiles

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