Class List

Here are the classes, structs, unions and interfaces with brief descriptions:
CHIPIT
CHIPIT_InPort
CHIPIT_OutPort
CHIPIT_Port
clk_info_s
vmm_atomic_gen< T, C, text >
vmm_atomic_gen_base
vmm_atomic_gen_callbacks< T, C, text >
vmm_atomic_scenario< T >
vmm_bottomup_function_phase_def< T >
vmm_broadcast
vmm_channel
vmm_channel_typed< T >
vmm_class_factory_base< classname >
vmm_connect< T, N, D >
vmm_consensus
vmm_data
vmm_debug
vmm_env
vmm_factory_base_pattern_info
vmm_factory_pattern_info< T >
vmm_fork_task_phase_def< T >
vmm_function_phase_def
vmm_group
vmm_group_callbacks
vmm_hw_arch
vmm_hw_arch_CHIPit
vmm_hw_arch_CHIPit_in_port
vmm_hw_arch_CHIPit_out_port
vmm_hw_arch_null
vmm_hw_arch_null_in_port
vmm_hw_arch_null_out_port
vmm_hw_in_port
vmm_hw_out_port
vmm_hw_version
vmm_inject_item_scenario< T, text >
vmm_log
vmm_log_below_iter
vmm_log_callbacks
vmm_log_catcher
vmm_log_catcher_descr
vmm_log_format
vmm_log_modifier
vmm_log_msg
vmm_log_watchpoint
vmm_mam
vmm_mam_allocator
vmm_mam_cfg
vmm_mam_region
vmm_ms_scenario
vmm_ms_scenario_election
vmm_ms_scenario_gen
vmm_ms_scenario_gen_callbacks
vmm_notification
vmm_notification_config
vmm_notify
vmm_notify_callbacks
vmm_notify_observer< T, D >
vmm_null_phase_def
vmm_object
vmm_object_iterTO DO
vmm_opts
vmm_opts_info
vmm_opts_info_wrapper
vmm_path_match
vmm_perf_analyzer
vmm_perf_analyzer_callbacks
vmm_perf_data
vmm_perf_tenure
vmm_perf_version
vmm_phase
vmm_phase_def
vmm_phase_impl
vmm_ral
vmm_ral_access
vmm_ral_block
vmm_ral_block_or_sys
vmm_ral_callbacks
vmm_ral_env
vmm_ral_field
vmm_ral_field_callbacks
vmm_ral_mem
vmm_ral_mem_backdoor
vmm_ral_mem_backdoor_callbacks
vmm_ral_mem_burst
vmm_ral_mem_callbacks
vmm_ral_mem_frontdoor
vmm_ral_reg
vmm_ral_reg_backdoor
vmm_ral_reg_backdoor_callbacks
vmm_ral_reg_callbacks
vmm_ral_reg_frontdoor
vmm_ral_sys
vmm_ral_sys_domain
vmm_ral_tests
vmm_ral_version
vmm_ral_vfield
vmm_ral_vfield_callbacks
vmm_ral_vreg
vmm_ral_vreg_callbacks
vmm_reset_xactor_phase_def
vmm_rtl_config
vmm_rtl_config_default_file_format
vmm_rtl_config_file_format
vmm_rtl_config_phase_build_cfg_ph_def
vmm_rtl_config_phase_def
vmm_rtl_config_phase_get_cfg_ph_def
vmm_rtl_config_phase_save_cfg_ph_def
vmm_rw
vmm_rw_access
vmm_rw_burst
vmm_rw_xactor
vmm_rw_xactor_callbacks
vmm_sb_ds
vmm_sb_ds_base
vmm_sb_ds_callbacks< INP, EXP >
vmm_sb_ds_exp_streams< DATA >
vmm_sb_ds_iter< INP, EXP >
vmm_sb_ds_pkt_stream< DATA >
vmm_sb_ds_pkts< DATA >
vmm_sb_ds_registration
vmm_sb_ds_stream_iter< INP, EXP >
vmm_sb_ds_typed< INP, EXP >
vmm_sb_version
vmm_scenario
vmm_scenario_election< T, text >
vmm_scenario_election_base
vmm_scenario_gen< T, text >
vmm_scenario_gen_base
vmm_scenario_gen_callbacks< T, text >
vmm_scheduler
vmm_scheduler_election
vmm_simulation
vmm_sql_db
vmm_sql_db_ascii
vmm_sql_db_sqlite
vmm_sql_table
vmm_ss_scenario< T >
vmm_ss_scenario_base
vmm_start_xactor_phase_def
vmm_stop_xactor_phase_def
vmm_subenv
vmm_subenv_version
vmm_task_phase_def
vmm_test
vmm_test_registry
vmm_timeline
vmm_timeline_callbacks
vmm_tlm
vmm_tlm_analysis_export< TARGET, DATA >
vmm_tlm_analysis_export_base< DATA >
vmm_tlm_analysis_port< INITIATOR, DATA >
vmm_tlm_analysis_port_base< DATA >
vmm_tlm_b_transport_export< TARGET, DATA >
vmm_tlm_b_transport_port< INITIATOR, DATA >
vmm_tlm_base
vmm_tlm_channel< T >
vmm_tlm_export_base< DATA, PHASE >
vmm_tlm_extension< DATA >
vmm_tlm_extension_base
vmm_tlm_generic_payload
vmm_tlm_initiator_socket< INITIATOR, DATA, PHASE >
vmm_tlm_nb_transport_bw_export< TARGET, DATA, PHASE >
vmm_tlm_nb_transport_bw_port< INITIATOR, DATA, PHASE >
vmm_tlm_nb_transport_export< TARGET, DATA, FW_PHASE, BW_PHASE >
vmm_tlm_nb_transport_fw_export< TARGET, DATA, PHASE >
vmm_tlm_nb_transport_fw_port< INITIATOR, DATA, PHASE >
vmm_tlm_nb_transport_port< INITIATOR, DATA, FW_PHASE, BW_PHASE >
vmm_tlm_port_base< DATA, PHASE >
vmm_tlm_reactive_if< DATA, q_size >
vmm_tlm_socket_base< DATA, PHASE >
vmm_tlm_target_socket< TARGET, DATA, PHASE >
vmm_tlm_transport_interconnect< DATA >
vmm_tlm_transport_interconnect_base< DATA, PHASE >
vmm_tlm_xactor
vmm_topdown_function_phase_def< T >
vmm_tr_record
vmm_unit
vmm_unit_buildph_phase_def
vmm_unit_cleanupph_phase_def
vmm_unit_configdut_phase_def
vmm_unit_configph_phase_def
vmm_unit_configtestph_phase_def
vmm_unit_connectph_phase_def
vmm_unit_finalph_phase_def
vmm_unit_reportph_phase_def
vmm_unit_resetph_phase_def
vmm_unit_run_testph_phase_def
vmm_unit_shutdownph_phase_def
vmm_unit_startph_phase_def
vmm_unit_startsimph_phase_def
vmm_unit_starttestph_phase_def
vmm_unit_trainingph_phase_def
vmm_version
vmm_voter
vmm_watchdog
vmm_watchdog_channel
vmm_watchdog_xactor
vmm_xactor
vmm_xactor_callbacks
vmm_xactor_iter
vmm_xactor_phase_def< T >
vmm_xactor_phase_def_base
vmm_xvc_action_block
vmm_xvc_event
vmm_xvc_event_all
vmm_xvc_event_any_all
vmm_xvc_event_local
vmm_xvc_event_mapped
vmm_xvc_manager
vmm_xvc_scenario
vmm_xvc_stop_on_event
xvc_action
xvc_manager
xvc_parse_cmd
xvc_xactor

Intelligent Design Verification
Intelligent Design Verification
Project: VMM, Revision: 1.2.0
Copyright (c) 2008-2010 Intelligent Design Verification.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts.
A copy of the license is included here:
http://www.intelligentdv.com/licenses/fdl.txt
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