Functions | |
| interface | bus () |
| Bus interface Block. | |
| interface | bus_A (input bit clk) |
| BusA interface Block. | |
| interface | bus_B (input bit clk, output logic foo) |
| BusB interface Block. | |
| template<WIDTH = 8> | |
| interface | bus_C (input bit clk, output logic foo) |
| BusC interface Block. | |
| template<WIDTH = 8> | |
| interface | bus_D (input bit clk, output logic foo) |
| BusD interface Block. | |
| template<WIDTH = 8, DEPTH = 20> | |
| interface | bus_E (input bit clk, output logic foo) |
| BusE interface Block. | |
| template<WIDTH = 8, DEPTH = 20> | |
| interface | bus_F (input bit clk, output logic foo) |
| BusF interface Block. | |
| interface bus | ( | ) |
| interface bus_A | ( | input bit | clk | ) |
| interface bus_B | ( | input bit | clk, | |
| output logic | foo | |||
| ) |
| interface bus_C | ( | input bit | clk, | |
| output logic | foo | |||
| ) |
| interface bus_D | ( | input bit | clk, | |
| output logic | foo | |||
| ) |
| interface bus_E | ( | input bit | clk, | |
| output logic | foo | |||
| ) |
| interface bus_F | ( | input bit | clk, | |
| output logic | foo | |||
| ) |
![]() Intelligent Design Verification Project: Test, Revision: 1.0.0 |
Copyright (c) 2008 Intelligent Design Verification. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included here: http://www.intelligentdv.com/licenses/fdl.txt |
![]() Doxygen Version: 1.5.8 IDV SV Filter Version: 2.4.0 Mon Jun 22 22:48:38 2009 |